Modern microprocessors include cache memories for reducing the latency associated with memory access instructions. The cache memory typically includes a data array that stores the actual cache lines of data and a tag array that stores the address tags associated with the cache lines in the data array. Each entry of the tag array also includes storage for a status of the cache line. The cache line status indicates, among other things, whether the corresponding cache line in the data array is valid and whether it has been modified since being allocated.
Additionally, modern microprocessors, particularly superscalar microprocessors, include multiple functional units that require access to the cache memory, such as distinct load and store units. The cache memory data and tag arrays typically have multiple ports so that each functional unit can access the arrays simultaneously to optimize performance. However, adding multiple ports to the arrays may significantly increase their size and power consumption. Furthermore, because the size of these arrays is often already relatively large, making them even bigger may make the task of floor-planning the microprocessor to include them even more difficult.
One solution to this problem is to replicate the tag arrays so that each functional unit has its own tag array, which allows the tag arrays to be single-ported. Although this solution may require more space on the microprocessor in the aggregate, because each tag array is smaller, it eases floor-planning, and may additionally facilitate power management because each tag array is separately power-manageable. However, a problem with having replicated tag arrays is that when the tag and/or status of a cache line needs to be updated, all the tag arrays are accessed to update the status in each of them. This consumes precious access bandwidth to the tag arrays and requires all the tag arrays to consume power during the updates.
Therefore, what is needed is a cache memory organization scheme that addresses these problems.